General Summary:
Job Area: Hardware Engineering (Design)
Job Function
The candidate would be joining a team with deep expertise in designing Modem IP within wireless sub-systems for market leading products. In this role, the candidate would be working on cutting edge next-generation Wireless PAN technologies (Bluetooth, UWB, Thread, Zigbee etc.) for connectivity solutions within mobile phones, wearables, IOT and Voice & Music chips. The candidate would be a part of Bluetooth IP Design team and will be involved in IP and sub-system development. The role requir
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Company : Qualcomm Technologies, Inc.
Job Area Engineering - Hardware
Location India – Bangalore
Job Overview - High-speed and Low-power 5G Modem Hardmacro Implementation
·Front-end implementation of complex 5G hardmacro designs in advanced process nodes
·Primary tasks include writing timing constraints, power-aware synthesis, power-aware formal verification, CLP, Primetime, PTPX, CECO
·Optimize datapath design for low-area, low-power and high-frequency, using advanced features in synthesis such as MCMM, SAIF, multibit mapping, self-gating, congestion reduction recipes, etc.
·Optimize PPA using the right tool options and stdcell libraries / memories
·Handle complex digital blocks with upto 4M gates in advanced process nodes from 2nm / 3nm / 4nm
·Work closely with RTL, DFT and PD leads worldwide to take a project from Post-RTL to Netlist release to MTO, and converge on area, timing, power and testability
Minimum Qualifications – 2-6 years experience in Digital ASIC / Processor Design with a leading chipset company
·Experience in Synthesis (FC, DC, Genus), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECO
·Experience in UPF based power intent and synthesis, handling MV checks and CLP waiver reviews
·Strong fundamentals in core areas: Microarchitecture, Computer Arithmetic, Circuit Design, Process Technology
·Strong communication skills to work with design teams worldwide
Education Requirements Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering
es working on IP & sub-system development, latest technology nodes and on all aspects of the VLSI development cycle: architecture, micro architecture, RTL design and integration. Close interactions with system architecture, verification, SoC Design, Validation, Synthesis & PD teams are required for design convergence.
Skills/Experience
3-6 years of experience in the design of complex ASICs
Strong expertise in RTL coding of complex designs using Verilog/SV
Exposure to low power design methodology and designs with multiple clock domains
Strong debugging, analytical skills and strong communication skills, both verbal and written
Hands-on experience in front-end design tools
Minimum Qualifications
Bachelor’s or Master’s Degree in Engineering in Electronics, VLSI, Communications or related field
3 years of VLSI industry experience in Digital Design
Preferred Qualifications
Exposure to Bluetooth/BLE Technologies and scripting languages like Perl and/or Python
Skills
RTL Design, Linting Tools, Synthesis, Timing Analysis, Low-Power Design
Minimum Qualifications:
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