Staff Engineer, Digital Design

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible.

Job Description:

We are seeking a skilled and experienced DFT Lead to join our VLSI design team. The ideal candidate should have a strong background in Leading the SoC DFT end-to-end activities, including DFT Architecture specification creation working with Functional/Product development and customer.

Job Location: Bangalore

Responsibilities:

• Lead end to end SoC DFT Activities
• Collaborate with other teams and define the DFT requirements and Architecture.
• Deliver the DFT STA constraint to Physical Design team and ensure the timing closure of the DFT logic.
• Collaborate with the design team to ensure efficient and effective testability of complex integrated circuits.
• Design and implement DFT features such as scan chains, compression, and built-in self-test structures to enhance testability.
• Conduct DFT DRC checks in RTL/Netlist database to ensure compliance with DFT guidelines and rules.
• Utilize Siemen’s DFT tool to perform DFT analysis and optimize testability metrics.
• MBIST Design (including repair) and Verification using Siemen’s EDA tool.
• Validation of DFT structures/patterns in RTL, Netlist with and without SDF.
• Work closely with the verification team to define and implement DFT verification plans.
• Analyze and debug test failures and collaborate with the test engineering team to resolve issues.
• Provide guidance and mentorship to junior DFT engineers.

Qualifications:

• Bachelor's/Master's degree in Electrical/Electronic Engineering, or a related field.
• 8-12 years of strong hands-on experience in DFT methodologies and SoC DFT lead experience.
• Strong knowledge of LBIST, ATPG, DFT DRC, Scan compression, Low power DFT Techniques, MBIST, Boundary Scan, Analog DFT, JTAG Architecture, DFT STA Constraint development.
• Hand-on experience/expertise in Cadence/Siemen’s DFT EDA tools for Scan stitching, DRC, ATPG, Coverage improvement, MBIST, Boundary Scan.
• Proficiency in scripting languages such as Perl, Tcl, and/or Python for automation.
• Solid understanding of digital design fundamentals, RTL coding, Lint/CDC, Low Power Checks and ASIC design flow.
• Excellent problem-solving skills and ability to work effectively in a team-oriented environment.
• Strong communication and interpersonal skills.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.