General Summary:
Micro-Arch, RTL Design ownership of SMMU IP for the next generation System-on-chip (SoC) for smartphones, tablets, and other product categories. System Memory Management Unit (SMMU) does virtual to physical address translation, dynamic allocation, and access control of DDR memory, designed as per ARM SMMU architecture spec
Job responsibilities include
Work with Hardware and Software teams to understand the design requirements, specification, and interface details for SMMU IP
Develop micro arch design specification optimized for performance, area, power, Software use cases
Implement design spec in RTL coding language, qualify code through all required quality checks like Lint, CDC, Synthesis/DFT/low power checks
Work with SoC level performance modeling team on latency, bandwidth analysis, fine tune HW configuration like cache, buffer sizing
Debug and root cause post silicon issues in collaboration with emulation, software test teams
Required skillset includes
VLSI logic design expertise
ARM system architecture, Memory Management, Virtual Memory concepts, Core sight architecture, power management fundamentals
Knowledgeable about on-chip interconnect protocols like APB/AHB/AXI/ACE/ACE-Lite
Strong debugging, Analytical and problem-solving skills
Good understanding of the ASIC design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
Communication and collaboration skills to work with a large world-wide design organization
Desired skillset includes
Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse
Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models
Working knowledge of Synthesis, DFT, LEC, functional cover points/assertions, formal verification
Minimum Qualifications:
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