Senior Verification Engineer

NXP Semiconductors N.V. (NASDAQ: NXPI) is the world leader in secure connectivity and processing solutions for embedded applications. NXP is solving the world’s most complex technology challenges to accelerate business innovation, enhance how we work, and advance how we live. 

AsiaPac "Design Enablement Engineering Support" team is focused on the implementation of methodology in close collaboration with the AsiaPac design teams and on the tactical support of all SoC design development. 

The candidate will contribute, within an international team, to the deployment and support, flows and tools of design of integrated circuits used in the company. The candidate will also be the main interlocutor of design teams to pro-actively understand their needs, to implement solutions that address the resolution of new technical challenges or recurring problems impacting the development of integrated circuits. 

 
Specific skills & knowledge: 

·Excellent knowledge on Digital Front End design flow for <20nm technologies. 

·         Experience in EDA tools associated to Digital FE from Cadence (Xcelium, Simvision, Verisium) and / or Synopsys (VCS, Verdi) is a must.

·Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog. 

·Skilled in EDA test regression tools associated to Digital Front End Flow as vManager cadence tools. 

·Exposure to Low-power design and UPF methodology. 

·Experience in front-end design of complex multi clock domain blocks. 

·Experience in Spyglass for lint and CDC checks. 

·Good Knowledge TCL / Shell / PERL / Cadence SKILL/ Python Scripting. 

·Good IT infra and LSF skills. 

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status.  

More information about NXP in India...