Senior SOC Design Engineer

NVIDIA System-On-Chip (SOC) group is hiring for a Senior SOC Design Engineer! The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand. We are looking for a star candidate with strong inclination in RTL integration and chip level front-end design, including padring, pinmuxing, SOC Assembly process, retiming etc. You must have a real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the chance to build sophisticated Tegra SOCs, work closely with chip management to set ASIC execution timelines & goals while directly interacting with System Architecture, unit-level ASIC, Physical Design, CAD, Package Design, DFT and other teams. Additionally, you will be involved in defining and crafting methodologies that build more efficient and flexible SOCs in future.

What you'll be doing:

• Drive SOC Assembly and design chip level functions for Tegra SOCs.

  
  

• Responsible for front-end design quality/correctness checks, reviews and driving those with multi-functional teams.

  
  

• Drive SOC execution across chip milestones working with all multi-functional teams to help define, track and drive complex dependencies.

  
  

• Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.

  
  

• Identify difficulties and inefficiencies in the front-end chip implementation process and propose and implement ideas to solve them.

  
  

What we need to see:

• B.Tech or M.Tech in Electronics Engineering.

  
  

• 5+ years of proven experience in chip design, specializing in SOC integration and design automation. Padring and fuse/floorsweep design experience is a bonus.

  
  

• Excellent analytical and problem-solving skills.

  
  

• Experience in RTL design (Verilog), System-On-Chip design/implementation flow.

  
  

• Strong coding skills in Perl, Python, or other industry-standard scripting languages.

  
  

• Exposure to various Chip Design Functions to be able to collaborate and solve complex multi-functional problems.

  
  

• Excellent interpersonal skills to work with multiple teams to drive consensus.

  
  

• Good teamwork spirit and collaboration skills with team members.

  
  

• Background in SOC Verification, Synthesis, Physical design and DFT is a bonus.

  
  

• Experience in RTL Build flows and Makefiles is a plus.

  
  

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.