Senior Principal Engineer - DFT ATPG Lead

• Leading DFT ATPG implementation, integration and verification of System-on-Chip (SoC) from initial specification till tapeout and production.
• Ensure Test Coverage Goals are met at SoC Level.
• Addressing test quality targets in DFT architecture and test pattern generation.
• Leading various aspects of Test architecture including Scan&ATPG, and post-silicon support
• Work with different functions like front-end design, verification and physical design to ensure production quality silicon.
• Support post-silicon activities, working with test engineering and validation teams.

• Master/Bachelor's Degree in Electrical/Electronic Engineering.
• Experience of 12+ Years in DFT with successful delivery of production quality chips.
• Senior SoC DFT engineers, with experiences in all aspects of DFT, including scan & ATPG, memory BIST, logic BIST, analog test, and post-silicon support.
• Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design.
• Self-motivated. Excellent written and verbal communication skill.
• Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components.
• Should be a team player and willing to work with cross functional teams in issues resolution.

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