Summary:
The Analog Design Enablement organization defines, develops and integrates flows and methodologies to assist worldwide the NXP designers of analog and RF circuits in the development of these circuits.
The focus of this position is on parasitic extraction (PEX) and netlist analysis for New Product Introduction (NPI). The methodology and flow aspects are based on industrial commercial tooling of well-known EDA vendors in the market.
Job Responsibilities
Collect requirements and specifications for Parasitic Extraction and Network Analysis with requesting design teams.
Work with PDK engineers, modeling engineers and process technology experts to optimize PEX accuracy.
Provide guidelines and recommendations to design teams for PEX setup and design options to ensure accurate extraction results and optimal simulation throughput.
Cooperate with designers to help them understand PEX output.
Understand network topology to provide recommendations for reduction, optimization and filtering of PEX results.
Maintain and expand the relation with EDA vendors to provide feedback on tool behavior, suggest improvements and be involved in beta programs.
Implement prototype technology definitions and LVS rules to assess the impact of improved modelling techniques.
Maintain and expand testcases to perform incoming inspection of new tool versions or new tools.
Develop / maintain a broad knowledge of technical developments in the domain.
Assist design teams in improving their Analog/RF designs for future applications.
Understand, define and implement PEX methodologies, PEX technologies and network reduction and manipulation techniques. You will be able to qualify PEX results and apply methodologies for PEX netlist analysis.
Assess the completeness of PEX results, find flaws in PEX setup and mitigate these by improving PEX setup or flow. You will understand LVS results and suggest improvements to PDK teams where required. You have a proficient knowledge of programming languages (Python, Perl, Skill and/or C++) and Linux, and are able to employ that in the analysis of PEX results and netlist screening.
Work together with analog/RF design experts, device physicists, EMC engineers, PDK engineers across NXP.
Maintain and expand relations with EDA vendors in the area of PEX and network analysis. You will be part of NXP’s worldwide team of experts in the area of analog design enabling.
Job Qualification:
Master's degree in Electronics engineering, Electrical Engineering, Applied Physics and/or an equivalent proficiency in parasitic extraction and network analysis
6+ years minimum of industrial experience in parasitic extraction, post-layout simulation and network analysis.
Industrial experience in Analog and RF design is a plus.
Skills in parasitic extraction and field-solvers with available commercial tools
Knowledge of Cadence Virtuoso OA design environment is highly recommended.
Familiar with the Analog – RF IC design process in general.
Knowledge with programming languages (Phyton, Perl) is a requirement, C++ or Skill is a plus.
Excellent communication/presentation skills and a team player
Proficient in communicating and writing technical documentation in English.
Able to work in a dynamic environment.
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