Company:Qualcomm India Private Limited
Job Area:Engineering Services Group, Engineering Services Group > Layout Engineer
General Summary:
Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.
Minimum Qualifications:
• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
• 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).
Experience: 4-6 years
Educational Qualification:
- B.E /B.Tech or M.E/MTech in Electrical and Electronics are preferred.
Role & Responsibilities:
As a RF layout engineer, you will be responsible for:-
- Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.-
- Proven hands-on experience in layout design and methodology development.
- Efficient programming skills in scripting languages like SKILL, Perl, Python, TCL, Shell, etc
- Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM checking-
- Co-work with designers across geographies on block level and top-level floor planning-
- Layout review for power/ground routing, electromigration, signal path check, differential and IQ matching, and signal coupling-
- Top-level layout integration and verification
Key Qualifications:
- Experience in custom RF/analog layout with extensive knowledge of deep sub-micron CMOS (14nm FinFET and below)
- Knowledgeable in layout techniques for device matching, minimizing parasitic, RF shielding, and high frequency routing
- Solid understanding of RC delay, electromigration, and coupling
- Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
- High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
- Knowledge of CADENCE layout tools
- Excellent communication skills and able to work with cross-functional teams
- Capability to lead other layout engineers for top-level integration
- Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems
- Scripting skills in PERL or SKILL are a plus.
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