Job Description
Scope of Responsibilities / Expectations
- Have good understanding of SoC Scan Architecture, Clocking, ATPG
- Have good understanding of test mode timing constraints.
- Able to Handle Spyglass DFT, Scan Insertion, ATPG and gate level simulations for multiple sub systems.
- Able to analyze DFT DRC and coverage analysis.
- Work with different functions like front-end design, verification and physical design to ensure production quality silicon.
- Able to guide juniors in the team.
Specific Knowledge/Skills
- Master/Bachelor's Degree in Electrical/Electronic Engineering.
- Experience of 5~8 Years in DFT with successful delivery of production quality chips.
- Must have gone through atleast one full SoC execution cycle.
- Experience in handling Spyglass DFT Checks at RTL and identifying DRC Fix
- Experience in handling Scan Insertion for complex sub systems using Fusion Compiler/Design Compiler.
- Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design.
- Self-motivated. Excellent written and verbal communication skill.
- Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components.
- Should be a team player and willing to work with cross functional teams in issues resolution.
More information about NXP in India...
Job Details
- Job Location
- India
- Company Industry
- Other Business Support Services
- Company Type
- Unspecified
- Employment Type
- Unspecified
- Monthly Salary Range
- Unspecified
- Number of Vacancies
- Unspecified