Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.
Job Responsibilities
Responsible for Corporate Application Engineering (CAE) activities in the Design for Test (DFT) Domain of VLSI systems
From a technical stand-point, understanding customer needs on DFT, involve and work with their projects for using right methodologies and Siemens tools for successful project completion
Provide DFT Tool support to all the existing customers. Help customers improve the productivity through efficient tool usage. Provide onsite tool support to customers as and when needed
Developing and delivering technical training on new features and product updates
Tracking and updating customer issues using defined
Siemens processes and tracking tools.
Developing Technical content for Siemens knowledgebase.
Involve and drive the Tool evaluation/benchmark; Technical product presentations; Methodology review; Tool deployment and adoption; drive competitive replacements, provide support to customers during critical project implementation phases.
Educational qualifications:
Required BE/B.Tech in Electronics & Communications Engineering (E&C), or Electrical and Electronics Engineering (EEE)
Work Experience:
4+ year’s relevant experience in DFT area of VLSI domain.
Technical skills:
In additional to possessing hands-on knowledge of DFT implementation and verification, the position would need excellent problem solving & communication skills able to work independently to solve complex problems and device new solutions and workarounds for customer issues.
Knowledge and experience with VLSI design, HDL Synthesis, VLSI Testing and design for testability.
Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred. In-depth understanding of Design for Test (DFT) structures is required. This includes ATPG/Scan/Compression based testing, Memory BIST, Logic BIST, IJTAG and Boundary Scan (1149.1/6). Knowledge of scan data compression methodologies with EDT is preferred.
Preferred experience in specific areas:
Operating Systems: UNIX, Linux, Sun Solaris.
Languages: Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++.
CAD Tools: Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Familiarity with Tessent flows and methodologies is a plus.
General/soft skills:
Work effectively with customers, internally with divisions and R&D
Ability to work autonomously
Strong verbal and written communication skills; good presentation skills
Excellent organizational and time management skills
Build and foster relationships with customer and peers with a positive attitude to win business success
Good problem solving and debugging skills, Willingness for technical sales
Should be a good team player
Job may require some domestic and international travel.
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