General Summary:
Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.
Minimum Qualifications:
Candidate needs to have hands on experience on various Power Management (PMIC) Module layouts, physical verification using Calibre Verification suite. Skill sets needs to include but not limited to the following:
Extensive floor planning and signal planning skills in Cadence Virtuoso IC201 and above. Layout Design for various analog circuits like: Linear and Switching Regulators, ADCs, DACs, CHARGERS, Envelope Trackers, APTs, High Current POWERFETS, OTAs, Error Amplifiers etc.
Strong understanding of submicron, deep-submicron, High Voltage CMOS processes.SOI process knowledge is an advantage.
Very strong analog layout fundamentals and basic electrical knowledge for layout development.
Strong physical verification debugging capability using Calibre Verification Suite. Create area and parasitic efficient layouts, with strong problem solving skills. Ability to perform in a dynamic, team oriented environment.
Well-developed organizational skills and the ability to multi-task.
Scripting knowledge in SKILL/PERL/SHELL is an advantage.
Strong communication skills for efficient delivery.
Team player skills to work with geographically spread team members
Create technical documentation and presentations.
Minimum Qualifications:
Graduation in Electrical or Electronics is preferred with 4+ years of exp.
Diploma with minimum 7 years of hands on layout development experience
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