Lead Design Engr - DFT

Your main duties will be:

• Will be responsible for Designing and Implementing DFT techniques (Memory BIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/Logic BIST) on complex SOCs to improve testability
• Test Modes implementation and verification, scan insertion including on-chip compression
• Implementing, integrating and verifying memory BIST and boundary scan
• Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test coverage and simulations at gate level with timing (SDF)
• Closing working with Test Engineer and Product Engineer team to understand testability requirement for zero-defect
• Post-silicon bring-up support
• Basic understanding of complete SOC design and flow
• Cross functional teams interaction for issue resolution
• Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability
• Mentoring new team members

 
We are looking for a candidate with these specific personal characteristic and qualifications:

• Bachelor's Degree in Electrical/Electronic Engineering
• 8-12 year(s) of working experience in DFT
• Must possess a strong knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation
• Must have a firm understanding and hands-on experience on industry
• standard DFT techniques: Memory BIST and Repair/ Scan/ On-Chip Compression/ At-speed Scan/Boundary Scan/Logic BIST in one or more complex SOCs
• Strong Knowledge/Understanding of Synthesis & STA
• Experience with silicon-bringup is a plus
• Should be a team player and willing to work with cross functional teams in issues resolution
• Creative problem-solving skills and the ability to logically break complex problems down to manageable components
• Self-motivated
• Good written and verbal communication skill
• Applicants must be willing to work in Noida

B.Tech/ M.Tech (ECE or Electrical)

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