Job Details:Job Description: Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
Qualifications:Qualifications:
Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 3 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 5 years of relevant industry experience.
Experience: Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification.
Experience in verification of design blocks (IP) for system-on-chip (SoC) components.
Experience in system verilog, and/ OVM or UVM based verification methodologies.
Experience in one/more of the following areas PCI_Express, USB, I3C, MIPI and /or AMBA standards (OCP, AXI, AHB etc.).
Knowledge of scripting, SVA.
Knowledge of IO Interconnect is a plus.
Knowledge of considerations for performance, power and cost optimization is desirable.
Expected to be thorough with general verification concepts with System Verilog/OVM/UVM- Writing test cases and making scoreboard/infrastructure changes to the environment.
Ownership/coding/enhancement of functional scoreboards/agents/sequences/monitors.
Knowledge in FPV is good to have.
Responsible for understanding architecture spec and deriving test cases / test plans.
Need to be a key team player, while being highly energetic and motivated, independent and self-driven (with minimal mentoring/handholding)- Expected to define functional coverage/code/hit it through sequence enhancement and newer/directed test.
Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
