Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
Bachelor in Electrical Engineering, Computer Engineering, and/or Computer Science plus 12-14 years of relevant work experience, Masters in Electrical Engineering, Computer Engineering, and/or Computer Science plus 10-12 years of relevant work experience, or a PhD in Electrical Engineering, Computer Engineering, and/or Computer Science plus 8-10 years of relevant work experience.
Experience owning a testplan and executing to verification closure.
5 plus years of experience in SystemVerilog, OVM/UVM.
Knowledge of AMBA protocols (AXI, AHB, APB). Knowledge of PCIe is a plus.
Knowledge of power aware verification is a plus.
Strong scripting skills.
Excellent verbal and written communication skills.
Exposure to Formal verification techniques is a plus.
Work Model for this Role