Job Details:Job Description:
In this position you will be working as part of a RTL design Team delivering soft IPs to next generation Server, Client SOC
Looking for Digital Design experience of around 8 to 12 years.
Knowledge of protocols PCIE/AXI/AHB/APB with strong RTL coding experience required.
Experience in tool runs to closure like CDC, RDC.
LINT, Synthesis and timing closure, LEC and Formal property-based verification for front end quality checks.
Understand SoC architecture and IP requirements.
Qualifications:Bachelors' or Masters' degree in EE or similar, with 8-12 years of relevant experience.
Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
