General Summary:
In this profile Responsible for the RTL Design and Integration of one or more IPs/sub-blocks as well as sub-system level design changes as per architectural requirement.
Working collaboratively with block designers, verification, architecture, implementation and post silicon teams for resolving issues and timely execution of project.
Collaborate with cross functional teams, debugging and identifying issues and providing workarounds and making recommendations on bug fixes. Additionally, candidate will also be responsible for meeting milestones, reviews, architectural documentation and post-silicon debug support.
Minimum 8+ years of work experience in ASIC RTL Design
Experience in Logic design/micro-architecture/RTL coding is a must.
Must have hands on experience with design and integration of complex multi clock domain blocks Experience in Verilog/System-Verilog is a must.
Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture
Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required
Understanding of Memory controller designs and microprocessors is an added advantage
Work closely with the Design verification and validation teams for pre/post Silicon debug
Hands on experience in Low power design is preferable
Experience in Synthesis / Understanding of timing concepts for ASIC is must
Minimum Qualifications:
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