Functional DV ( Clock/Power) Verification Sr Engineer & above levels

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Description

Qualcomm Graphics HW team in Bangalore is responsible for developing and delivering GPU solutions which are setting the power and performance benchmark in mobile computing industry. In this role of Graphics Verification Engineer, you will be verifying the Clock and power management module with design features for low power.

The responsibilities will majorly include:

• Understanding of GPU power and clock domains with power-up/down sequences
• Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging  simulations and achieving all coverage goals
• Develop test plan to verify sequences and design components for Clock and power management modules.
• Explore innovative  DV methodologies (formal and  simulation ) to continuously push the quality and efficiency of test benches

Successful candidate will be  required to collaborate with worldwide design, silicon and architecture teams to achieve all project goals. Hence, we are looking for candidates with strong communication skills.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Minimum Qualifications

Minimum 3 -13 years of design verification experience
* Senior positions to be offered to candidates with proven expertise in the relevant field

Preferred Qualifications *

3+ years industry experience with below skillset :

• Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology
• Experience in formal / static verification methodologies will be a plus
• Basic understanding of low power design techniques
• Good understanding of  design components such as clock gates, level shifters, isolation cells and state retention cells.
• Experience with Synopsys NLP (native Low Power) tool.
• Experience with scripting languages such as Perl, Python is a plus

Education Requirements

BE/BTech/ME/MTech/MS Electrical Engineering and/or Electronics, VLSI  from reputed university preferably with distinction

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