DSP IP SS Design Verification - Sr Lead Engineer

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Summary:          

• Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP IP
• HEXAGON DSP team is responsible for delivering high-performance DSP cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space
• Qualcomm is the largest fabless design company in the world, generating over $15 Billion in annual revenues from chipsets and royalties from intellectual property. Qualcomm provides hardware, software, and related services to nearly every mobile device maker and operator in the global wireless marketplace

 Job Responsibilities: 

• Drive design verification of DSP Subsystem IP by working with a global DSP design team involving architecture, and power  teams
• Implement and improve System Verilog Testbench Architecture
• Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency
• Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals
• Hand-on simulations and debug
• Complete all required verification activities at IP level and insure high quality commercial success of our products
• Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification
• Responsible for power aware RTL simulation

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Skillset/Experience:          

• 5-8 years’ experience in processor/ASIC design verification
• Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification.

• Expertise in System Verilog Testbench Architecture and implementation
• Expertise in UPF and PA RTL simulations

• Experience in VERA/System Verilog, simulators from Synopsys/Mentor/Cadence

• Solid analytic and debugging skills, strong knowledge of digital design and good understanding of Object-Oriented Programming (OOP) concepts
• Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and (HDL) such as Verilog, SystemVerilog
• Experience in AMBA, AHB, AXI , APB  and debug protocols
• Scripting/Automation Skills — Perl, Python, Shell, Make file TCI
• Experience is verification of Processor subsystems (ARM/DSP) is preferred
• Should have excellent inter-personal and communication skills

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