General Summary:
Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques.
Primary responsibilities will include,
Interface with design team to ensure DFT design rules and coverages are met.
Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.
MBIST verification (including repair), test pattern generation through Mentor tool.
ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing cornersimulations.
Workwith the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
Responsible for supporting post silicon debug effort, issue resolution.
Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE.
Developing, enhancing and maintaining scripts as necessary
Minimum Qualifications:
Minimum of 1-6 years’ experience in ASIC/DFT– simulation and Silicon validation
Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement
In depth knowledge and hands-on experience in ATPG - coverage analysis.
In depth knowledge of Memory verification, repair and failure root-cause analysis.
Experience with any of these tools is required
ATPG -TestKompress
MBIST - MentorETVerify
Simulation -VCS(preferred), modelsim.
Expertise in scripting languages such as Perl, shell, etc. is an added advantage
Ability to work in an international team, dynamic environment with good communicationskills
Ability to learn and adapt to new tools, methodologies.
Ability to do multi-tasking & work on several high priority designs in parallel
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