Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY23 and approximately 26,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible. Learn more at www.analog.com and on LinkedIn.
The Engineering Enablement Org is part of the CTO at Analog Devices and is responsible for providing best-in-class tools, flows, methodologies and support to engineering teams across the company to accelerate product development. This position is for an opening in the Systems Verification and Validation (SVV) team within the Engineering Enablement org, focused on the Verification IP Development. Overall, SVV team works to define and promote the adoption of design verification best practices, including Metric-Driven Verification, UVM, Verification IP, DV tools, Formal, FuSa, Security, Portable Stimulus, Emulation and FPGA prototyping technologies.
Job Responsibilities- Architect, design and develop best-in-class UVM/C based Simulation, Accelerated and Formal Verification IPs for latest generation complex protocols.
- Develop reusable protocol Conformance Test Suite (CTS), Spec annotated Verification plan (vPlan), Portable Stimulus compatible sequences and userguide.
- Integrate VIPs into ADI's UVM Testbench Generator and make it compatible with ADI DV ecosystem.
- As a protocol & VIP expert, support engineering DV teams to adopt in-house and vendor VIPs (including Accelerated VIPs, Formal VIPs), create & deliver protocol training materials, assist in debugging VIP/protocol issues, share learnings at internal and external conferences.
- Explore & apply innovative DV methodologies to improve the existing solutions further.
Job Requirements- MTech in VLSI/Electronics/Electrical Engineering with 3+ years of relevant industry experience (or) BTech with 5+ years of experience (or equivalent experience).
- Proficient in UVM VIP development and/or IP/Sub-system/SOC verification
- Should have developed complex UVM testbenches from scratch
- Proficient in digital design, digital verification fundamentals, SV, SVA, UVM and MDV.
- Proficient in Python/Perl (C/C++ is a plus)
- Strong analytical, problem-solving and debugging skills
- Highly motivated and team player
- Ability to manage multiple tasks and work effectively in a fast-paced environment
- Excellent communication skills
- Exposure and technical familiarity with commonly used protocols - AMBA, SPI, I2C, etc (JESD, UCIE, ASA is a plus)
- Exposure to hardware emulation platform (Palladium)
- Exposure to Matlab/Simulink
- Exposure to simulators (XLM/VCS etc), Debug solution (Verisium/Verdi), version control software (P4, GIT, etc) and IDE (DVT, etc)
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days
