ASIC Physical Engineer Staff

Job Specification The successful candidate will work with internal Design and Methodology teams to lead and implement Physical Designs of multiple blocks of complex ASICs. This position requires a good understanding of the physical design flow from RTL to GDS and several chips tapeout experience. The candidate should possess in-depth knowledge and experience in physical synthesis, design planning, floor planning, place & route, static timing analysis, design closure, and physical verification.

Responsibilities

• Lead/implement multiple blocks, potentially mentoring or leading a small group of engineers.
• Track block convergence and effectively communicate with Fullchip or front-end teams for smooth block closure.
• Handle critical block closure in firefighting situations.
• Responsible for all aspects of Physical Design for Fullchip/Blocks, including Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, and Low Power solution development & implementation.
• Preferably have sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, and internal tools & flow.
• Work closely with the methodology team to solve implementation challenges and provide inputs to improve the Physical design flow.
• Experienced in design automation.
• Understanding of Timing constraints, SI prevention, Power reduction.
• Must have prior experience with Synopsys/Cadence/Mentor place and route tools.
• Must have completed design in 16nm and or 7nm.
• Proficient in Unix/TCL/Perl.
• Good communication and presentation skills. Requires good interpersonal skills and problem-solving ability.

Minimum Qualifications

• 8+ years experience in ASIC physical design.
• Experience with block implementation, extraction, timing, and or full-chip designs.
• Strong communication skills.
• Strong hands-on TCL/Perl development skills.