Staff Verification Engineers
Si-Vision staff engineers are responsible for gathering verification requirements, contributing
to the verification planning, implementing the verification environment, running simulations,
and achieving coverage targets.
#Qualifications:
- B.Sc.,/M.Sc., in Electronics & Communication Engineering.
- 7+ years of experience.
- Excellent knowledge of coverage-driven verification concepts.
- Excellent knowledge of advanced verification methodologies (OVM/UVM/VMM).
- Proficiency in architecting, designing, and implementing verification environments.
- Strong experience in developing and maintaining block-level and top-level verification environments for digital systems.
- Excellent debugging skills in both functional and gate-level simulations.
- Strong programming skills in object-oriented languages (C++, Java, or Python).
- Experience with Assertion Based Verification languages (SVA, PSL).
- Knowledge of scripting languages (PERL, TCL, Shell script).
- Experience with power-aware verification and UPF writing is a plus.
- Experience with Formal Verification is a plus.
- Proficiency in using verification planner tools to monitor progress.