ASIC Emulation Engineer

It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. Cisco Common ASIC Group is looking for a ASIC Emulation Engineer to work on the shift left methodology to find post silicon performance and functional issues before tape out for our next generation switching systems.

As part of the ASIC team, you will be developing the emulation env, build netlists and use the same to speed up the development cycle and find potential ASIC issues during pre-silicon phase. There are only a very few teams worldwide that implement such devices. Every time you access the Internet, chances are, your data's been through one of our switches.

You will work with Cisco’s best-in-class switching solution team. Our team is responsible for driving integration of the Nexus systems and ACI with software, including OpenStack, Docker, and Open vSwitch, to help our customers build multitenant clouds.

You are a dedicated, motivated ASIC emulation/verification engineer to join the team and contribute to the verification of very complex ASICs. You have a Design Emulation background with hands-on experience with emulation platforms like Veloce/Palladium/Zebu. You will be fluent in System Verilog or Verilog to work on the Emulation infrastructure development work.

In-depth knowledge of C++, scripting, as well as ASIC design and verification flow is your strength.

You’ll be part of Cisco Common ASIC Group, focusing on developing and testing various emulation flows and contributing to different aspect of ASIC verification for bug free Silicon.

You will collaborate closely with the design team and the hardware team to verify the ASIC in emulation and during ASIC bring up.

• Develop state-of-the-art emulation environments that will be used to evaluate the performance and functionality of multi-terabit systems.
• Developing emulation infrastructure using C/C++ and TCL
• As a team member, work closely with the design, DV, power, and post-silicon diagnostic teams.
• Assist with test plan design, test implementation, and debugging during the pre-silicon emulation process.
• Develop tests to generate complex traffic, performance scenarios to catch potential post Silicon issues during Pre-Silicon phase.
• Work with leading emulation vendors to troubleshoot issues.

• Master’s degree in EE (Electrical & Electronics) or CE (Computer Engineering) with 2+ years of relevant experience.
• Bachelor’s degree in EE or CE and 3+ years of relevant experience.

Mandatory Skills:

• 1+ years of emulation experience on platforms such as Palladium, Veloce, or Zebu as well as experience with compilation, debug, performance testing.
• Hands-on RTL development for Emulation prototypes and proficiency in Verilog, System Verilog.
• hands-on experience with C/C++ and TCL infrastructure development
• familiar with System debug tools like gdb, waveform debuggers.

• hands-on experience with scripting programs (e.g., Python, Perl or similar)
• Strong communication skills and ability to work as a team.
• Post Silicon functional validation or debugging experience is a plus.
• Knowledge of protocols e.g. PCie, I2C, Ethernet packet headers, Ethernet protocol is preferred.
• Good written and verbal communication skills
• Collaborative and team-focused, with the drive to learn and grow

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