Job Details:Job Description: Responsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.
Qualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must be pursuing a Master's degree in the field of electronics engineering or hardware engineering, Electrical and/or Computer Science/Engineering or related fields with knowledge in: Digital circuit design, including CMOS combinatorial logic and sequential element design and layout. Good understanding of device physics. Strong Python programming and automation skills. Excellent collaboration skills across geographically distributed teams and being able to handle ambiguity while developing expertise in new areas and delivering excellent, quantifiable results will be key to the success in this role. The successful candidate must possess excellent written and verbal communication skills, strong customer/result orientation and the ability to work with external, internal partners and with EDA vendors in a flexible manner. Preferred Qualifications:
Experience with Industry standard ASIC tools - Design Compiler, Genus, Tempus, ICV Experience in digital circuit design, front end model creation and functional verification. Digital circuit design, including CMOS combinatorial logic and sequential element design and layout. Good understanding of device physics. Experience with standard cell library characterization, liberty models and cross validations with front end models and liberty models. Experience working with EDA vendors to drive new features and capabilities. Knowledge of industry-standard EDA tools for VLSI circuit and layout design. Experience working in the Linux environment and its development tools. Standard cell level PPA modeling, simulation, and ROI analysis. Experience in CMOS power modeling and cell level optimization. CMOS and standard cell level device variation and Aging analysis. Engineering acumen and analytical skills. Debugging skills. Customer oriented and able to work in a dynamic environment. Requirements listed would be obtained through a combination of industry relevant job experience, and or schoolwork/classes/research.Job Type:Student / Intern
Shift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Legal Disclaimer:It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.
