Job Summary
The Verification role will involve many aspects of Functional, Performance verification using most effective methodologies in context of Module/Subsystem/SoC /System Level. A strong ability to map requirements into a traceable verification plan is important. The ideal candidate will partner with local and global SoC and IP developers to drive best practices with a target of ongoing productivity improvement. A “zero-defect” mindset is a key enabler. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation, formal verification and emulation, debugging failures and creating simulation cases for various studies.
Expectations include: -
Team leadership with technical guidance and tracking
Verification planning.
Verification test bench development, tuning and implementation.
Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs;
Development of direct and constrained-random stimulus using c , SV
Understands and analyzes RTL code, functional, assertion coverage results.
Understands Develop functional coverage.
Understands and develops system Verilog assertions.
Understands and implements formal verification methods.
Strong skills in debug, failure re-creation and root cause analysis
Applicant should have efficient debugging and logic skills.
Job Qualifications: -
C and UVM/SV based Test environment,
Understanding of the design/architecture and ability to debug RTL/Gate netlist is MUST
Coverage driven Verification for addressing Functional, Performance requirement of the SoC, regression management
Microcontroller architecture, ARM Cores, Interconnect (NIC, FlexNoC), Cache Coherency,
Bus Protocols like AHB/AMBA, AXI, ACE
Following skills will have additional value
o Memory controllers (Flash, SRAM,DDR3/4/LPDDR)
o Protocols like PCIe, MIPI, GPU (Graphics processing), Ethernet,
Serial / Quad flash o Formal verification methodologies and Apps,
AVIP, PinMuxing Verification, Randomization
o Low Power intent verification using UPF
o Exposure to pre silicon validation/emulation (Veloce, Zebu)/FPGA Prototyping would be a plus
Experienced SoC Verif Engineer with hands-on exposure of at-least 2 of the following skill sets:
1. Working experience of SoC Verif of Multi core SoCs on UVM TBs.
2. Working experience of ARM based Debug sub-system verification.
3. Working experience of Safety / Security Verification of SoCs.
4. Working experience of Low Power Verification .
5. Working experience of NoC Verification.
6. Working experience of Clock/Reset Archi of SoC.
7. Working experience of generating Functional Tester Patterns for ATE.
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