Job Details:Job Description:
Looking for enthusiastic, motivated and self-driven engineer in area of Power Analysis and Signoff who can take care of
- Understanding and Defining Chip Power & Performance Targets
- Analyzing FSDBs for various design power scenarios and extracting the right activity windows
- Running Power Estimation and Analysis at block level and roll-up total power for SoC
- Working with Architecture, Design and Implementation teams for power optimization
- Running LP checks at block and full chip level, analyzing the logs/reports and deliver quality results
- Work closely with the FE & BE teams for overall Power Convergence and Low-Power Sign-off of the design for Tape-out
Qualifications:BE/ME in Electrical Engineering with 8+ years of experience in Logic Design, Synthesis and Low Power Design/Implementation for complex multi-million gate SoCs Expertise in power analysis using PT-PX/Prime Power Experience in Verdi tool for FSDB analysis Experience in power analysis using Power Artist tool is a plus Experience in industry standard tools LP checks, PTPX for power estimation etc. Strong analytical and problem-solving skills Expertise in Tcl, Perl/Python is requiredJob Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
