Contribute to a centralized Signal Integrity team that supports next-generation cutting-edge technologies.
Deliver system-level signal integrity solutions for large complex high-speed systems, boards, and packages.
Take ownership of all aspects of signal integrity design, from design feasibility to product validation.
Develop SI rules, build on design guides and checklists, review design implementation, create test plans, and document characterization and measurement reports.
Improve and optimize design margins through interconnect, timing, and crosstalk analysis, 3D EM, and channel simulations for high-speed designs.
Understand SI trade-offs, the impact of various aspects of system design, and provide timely technical assessments and progress updates to SI Management.
Design and characterize test structures and channel models to correlate simulations and measurements for serdes and interconnects.
Collaborate with cross-functional teams such as HW designers, layout Engineers, SW Engineers, MFG Engineers, ASIC Engineers, ODMs, and vendors.
Be flexible to accommodate changing design requirements, capable of simultaneously working on multiple programs and assignments.
Be a team player, share technical knowledge within the team, leverage best practices, focus on quality, and continuous improvement.
Preferred Skills & Experience:
8+ years of relevant experience in Signal Integrity Design and Validation.
Bachelor’s / Master’s degree in Electronics / Electrical engineering or equivalent.
Self-motivated, ability to contribute independently as well as in a team environment that is matrixed and spread across geography.
Self-learner, strong problem-solving, board, and system-level lab bring up, debugging, and characterization skills.
Excellent oral and written communication skills, capable of presenting concepts, analysis, and updates to larger teams and forums.
Knowledge of Electromagnetics and Transmission line concepts, reflection and terminations, timing and jitter, crosstalk and noise, channel modeling, and serdes equalizations, PDN, and decoupling.
Familiarity with PCB stack-up design, best practices, trade-offs in line geometries, PCB materials and surface finishes, vendor capabilities, and manufacturing process.
Experience with lab equipment such as high bandwidth real-time and sampling Oscilloscopes, phase noise analyzers, TDR, VNA, spectrum analyzers.
Proficient with simulation and analysis tools like ADS, HFSS, HSPICE, Sisoft QSI, QCD, Cadence Allegro, Sigrity, PowerSI, MATLAB, etc.
Experience with common SI simulation models such as IBIS, IBIS-AMI, S-parameter, COM analysis, etc.
Knowledge of interface standards such as DDR 3/4, PCIe gen 2/3, 10GKR, SATA, XFI, XAUI, CAUI, CDAUI, etc.
Experience with 56G PAM4, 25G, and 10G NRZ serdes technologies - simulation, bring up, debug, measurements, optimization is a plus.
