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Job Details:Job Description: Delivers power integrity solutions for large, complex highspeed platforms, boards, packages, and silicon. Develops and analyzes power delivery networks including 2D and 3D model extraction and noise analysis across die/C4 bumps, silicon, package, sockets, and boards. Defines power grid specification and power and area targets to achieve the best balance of power integrity and performance. Develops test structures, electrical analysis methodology and verification plans to address challenges. Performs measurements to characterize power noise profile across frequency, ground bounce, and other key metrics to verify power delivery network after design and correlate back to presilicon analysis/estimations. Applies knowledge of power integrity design and tradeoffs to perform simulations of power network, guide package, and platform physical implementation. Ensures that ondie power noise meets SoC and other key platform ingredient functionality and performance. Develops and delivers platformlevel power shapes and decoupling solutions as part of the platform design guide to the end customers. Derives platform level specifications from silicon specifications, ensures package/platform pathfinding to converge on feature set/form factor, and VR performance characterization. Collaborates with the silicon integration team, die floor planners, and package design team to optimize the ondie decoupling partitions and implement the package decoupling scheme and voltage regulation for package/die.Qualifications:
  • Candidate must possess a Bachelor 's degree in in Electrical/Electronics/Computer Engineering with 10+ years of experience, a Master 's degree with 8+ years of experience or a PhD with 5+ year of experience
  • Strong background in power integrity design or related field ex: Power electronics. Has applied it to actual designs in the industry or academically.
  • Strong knowledge of different power supply rail interfaces ex: CPU or GPU Cores, DDR, PCIE, USB, and SERDES
  • Experience in power integrity industry simulation tools such as HSpice, Sigrity Tools ex: PowerSI/PowerDC, Matlab, 3-D solvers, etc.
  • Package/board routing CAD tools such as Cadence Allegro and Mentor Graphics.
  • Working knowledge of board-level system architecture, basic silicon design and package
  • Ability to design the power solution with constraints that include cost, schedule and design space
  • Understanding of other technical areas like Signal Integrity, thermal design, electronics microprocessor packaging circuit design, PCB manufacturing, etc.

Preferred skills:


If you have leadership experience, that will make you stand out from others. Can run technical meetings, mentor other engineers, and take full ownership of product design. This would be on top of doing design and analysis.


Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role


This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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