Summary:
STA & Sign off Methodology Engineer with min 6 years of experience with expertise in STA tools who can support timing and Power analysis & closure while making sure a seamless use of Foundation IP solutions.
Responsibilities:
The STA and Methodology Engineer is expected to work closely with the Foundation IP teams (Standard cell, IO, and Memories teams) and NXP NPI design teams spread across various BL's to support timing and Power analysis and closure while making sure a seamless use of Foundation IP solutions.
Expected to find solutions to the technical problems pertaining to RTL2GDS Chip lifecycle (mainly focussing on STA, derates and margining) etc.
Able to leverage the state of the art industry standard tools to support above.
Able to solve SoC design challenges in CDC (Clock domain crossing) and PDC (Power Domain Crossing) and in the Gate Level simulations.
Prepares design specifications, analysis, and recommendations for presentation and approval.
May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services.
Qualification:
6+ years of experience in Timing Analysis (Synthesis, STA, CTS, ECO etc.) Also understanding and experience with: STA tools (Cadence Tempus and/or Synopsys PrimeTime, SPICE analysis, Scripting (Tcl, Python), Statistical analysis experience a plus (R programming)
Working knowledge of liberty models (NLPM, AOCV, CCS(P), ECSM, LVF etc)
Overview of circuit and MC simulations, Layout Dependent effects, RTL2GDS flow.
Good understanding of CMOS and FinFET technologies.
Good understanding of State of the art EDA tools from Siemens, Cadence and Synopsys including Simulation, and Characterization work.
Knowledge and experience with Characterization methodology a plus
B.Tech/MS/M-Tech degree in Electrical/Electronics/VLSI Engineering or PhD (Electronics/Electrical/VLSI etc.)
More information about NXP in India...