NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.
Take part in top level floor plan and clock planning.
Optimize, together with CAD signoff flows and methodologies.
Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.
Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
3-8 years of experience in physical design and STA
Proven experience in RTL2GDS and STA design and convergence
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)
Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required.
Great teammate.
NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!
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