General Summary:
Experience in Logic design /micro-architecture / RTL coding is a must.
Must have hands on experience with SoC design and integration for complex SoCs.
Experience in Verilog/System-Verilog is a must.
Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.
Understanding of Memory controller designs and microprocessors is an added advantage
Hands on experience in constraint development and timing closure • Work closely with the SoC verification and validation teams for pre/post Silicon debug
Hands on experience in Low power SoC design is required • Hands on experience in Synthesis / Understanding of timing concepts for ASIC is required.
Minimum Qualifications:
Bachelors / Masters degree in electrical or electronics engineering with 1-3 yrs of experience is preferred
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