- Strong understanding of critical digital design principles, static timing analysis including setup and hold timing, clock skew, and clock domain crossing (CDC) etc.
- Hands-on experience on one/both STA Tools – Synopsys Primetime & Cadence Tempus.
- Experience of Timing Signoff for Block & SOC ( Flat & Hierarchical design ), Block Level IO budgeting, Timing ECO Generation – manually & using tools,
- Working knowledge in developing and maintaining timing constraints (SDC files) for functional and test modes with debugging skill for any issue.
- Good Understanding of Industry Standard IO/AC Spec , their translation to constraints and closure – JTAG, ENET,..
- Proficiency in any/more of scripting languages such as TCL, Perl, and Python for automating design flows and improving productivity.
- Ability to debug and solve any timing or constraints issue without/minimal supervision and working with team.
Experience - 10-12 Yr
Qualification - B.Tech/M.Tech
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