Principal Digital Verification CAD Flow Engineer

Summary:

The mission of the Design Enablement organization is to work closely with product design teams across the company to define and develop advanced EDA tools, flows and methodologies, and disseminate best known methods to support NXP product design world-wide.

Job Responsibilities

• Work closely with design/verification teams.
• Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.
• Drive automation techniques and ensure code re-usability across projects.
• Capability to work in an international team, align to global needs while taking ownership of a sub-domain. 
• Work on Power Intent Standards UPF

• Work on Static Power checks with tools like VCLP /conformal/JGLPV
• Verify Low Power features using power aware tools
• Work on power estimation features.
• Debug design issues and propose fixes (if applicable)

Job Qualification:

• Masters in Electronics/Electrical Engineering (a relevant experience with minimum 12 years in a semiconductor or high technology RD environment would be appreciated)
• Knowledge of SOC architecture and use cases
• Knowledge of functional/formal verification
• Expert knowledge platform level flow development using Object Oriented Programming preferably with Python
• Expert knowledge of verification tools such as VCS/Execution Manager and/or Xcelium/vManager

• Expert knowledge of verification methodologies such as the Universal Verification Methodology (UVM)
• Experience in low power verification methodologies is an added advantage
• Exposure to IP/SOC verification with C/ASM will be an added advantage.
• Experience in Object Oriented Software/Flow development with PYTHON or PERL/TCL
• Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills

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