Job Details:Job Description:
- Responsibilities may be quite diverse and are technical in nature.
- Creates bottoms-up elements of chip design including but not limited to cell, and block-level Semi-custom layouts, FUB-level floor plans, abstract view generation, RC extraction and schematic-to-layout verification, reliability verification and debug using phases of physical design development including parasitic extraction, custom polygon editing, auto-place and route algorithms, floor planning, full-chip assembly, packaging, and verification.
- Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
- Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments.
- Requires expansive knowledge and practical application of methodologies and physical design.
Qualifications:Education:
- Candidate should possess a Bachelors degree in Electronics, Electrical engineering or equivalent
Experience/Skills:
Additional qualifications include:
- Basic understanding of layout design and verification
- Basic knowledge of ICC2 tool
- TCL scripting would be added advantage
Job Type:Intel Contract EmployeeShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Business group:Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
