General Summary:
SoC Interconnect for the next generation System-on-chip (SoC) for smartphones, notebooks, smart glasses, tablets and other product categories. This position includes but no limited to:-
NoC Systems lead and is part of BDC infrastructure (NoC/Interconnect) core team
Responsible for system requirement collection, use-case understanding and preparing specification for interconnect working with adjacent IPs
Actively work with QPA team, SoC team, verification team, physical design team, Soc Floorplan, core teams and various other interconnect teams in various other sites
Partner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptions
Remains abreast with next generation ARM/Amba specification, PCIe specification, QNoC changes and Low Power Technology changes to guide and influence the NoC Design, Verification, Power and Physical Design teams in improving their KPIs, processes leading to better Qualcomm products at efficient NRE
Advises and leads small groups of less experienced engineers in evaluating various design features to identify potential flaws, compatibility issues, and/or compliance issues; reviews design evaluations conducted by less experienced engineers
Troubleshoots multiple advanced issues with NoCs; uses a variety of debugging tools and methods
Exercises exceptional creativity to innovate new ideas and develop innovative NoC systems and IP solutions without established objectives or known parameters
Minimum Qualifications:
7 to 12 years of experience in SoC design/Systems, NoC design/Systems
Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts
Good knowledge of Digital Design and RTL development
Hands-on experience with SoC Design, Verilog RTL coding
Understanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization
Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification and silicon debug
Working knowledge of Lint, CDC, PLDRC, CLP etc
Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
Should possess effective communication and leadership skills
Minimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering. PhD in Computer Science, Engineering, Information Systems, or related field and 15+ years of Hardware Engineering or related work experience is welcome
Minimum Qualifications:
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