LEAD PHYSICAL VERIFICATION ENGINEER

 You will be a part of the Automotive and Industrial Solutions Group which is a global leader in the design, manufacturing and marketing of Microcontrollers (MCUs) and Embedded Processors in the Automotive, Consumer and Industrial markets

 You will be responsible for:

• Complete SoC flat Physical Verification sign-off like LVS, DRC, Yield enhancement (DFM), Antenna, ERC, PERC, ESD etc
• Understanding all DRM rules and ability to give early design feedback to ensure correct by construct design.
• Floorplanning at chip and block level.
• Package Closure : Padring creation for Flip chip and Wirebond Packages.
• Work closely with the block owners to achieve Physical Convergence through systematic fixes and minimal manual effort.
• Close interaction with worldwide team members apart from SOC team (IO/ESD/Systems/IP design teams/Package Team/validation)

We are looking for a candidate with these specific personal characteristic and qualifications

• Master/Bachelor's Degree in Electrical/Electronic Engineering
• 7-10 years of working experience in Physical Integration
• Must have a firm understanding and hands on experience into Physical verification at block and chip level DRC, LVS, DFM, Antenna, ERC, PERC, ESD etc
• Physical verification flow automation exposure will be an added advantage.
• Experience in PnR tools like ICC2/Innovus with regards to physical convergence
• Must possess a strong knowledge of Physical design flow
• Should be a team player and willing to work with cross functional teams in issues resolution
• Creative problem-solving skills and the ability to logically break complex problems down to manageable components
• Self-motivated and Good communication skill

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