Your primary responsibilities include:
· Verification Environment Development: Guide the development of verification environments, testbenches, and test cases for IBM server processors, SOCs, and ASICs.
· Collaborative Debugging: Collaborate with design teams and key stakeholders to debug and resolve logic design issues, ensuring the delivery of high-quality designs.
· Coverage Closure: Drive verification coverage closure by developing comprehensive test plans and strategies, ensuring thorough verification of IP/unit/block-level designs.
· Programming: Utilize object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios and automate verification processes.
· Ongoing Skill Development: Develop proficiency in IBM functional verification tools and methodologies, staying updated with the latest advancements in the field.
Required Technical and Professional Expertise
· Functional Verification Experience: Extensive experience in functional verification of processors or ASICs, demonstrating a deep understanding of verification methodologies.
· Computer Architecture Knowledge: In-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification.
· Multi-Processor Cache Coherency: Experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems.
· Gate Level Simulation and Emulation: Proficiency in gate level simulation and emulation techniques, facilitating thorough verification of designs.
· Functional Verification Methodology: Expertise in functional verification methodologies such as UVM/OVM/System Verilog/SystemC, ensuring effective verification of designs.
Preferred Technical and Professional Expertise
· Advanced Verification Techniques: Familiarity with advanced verification techniques such as formal verification or assertion-based verification, enhancing verification thoroughness and efficiency.
· Experience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL, enabling seamless collaboration with design teams and enhancing verification effectiveness.
· Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design abstraction.