DFT CAD Sr Lead Engineer

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Qualcomm Global CAD Organization is looking for DFT/ATPG Methodology development lead to develop DFTCAD methodologies for Qualcomm’s 5G products in advanced FinFET semiconductor process nodes. In this role, you will be a member of a global technical team working with SOC Design, DFT, Product and Test, and Diagnostics teams, as well as EDA Tool vendors to develop world-class DFT methodology solutions.

Key Responsibilities

• Lead DFT ATPG flow development, integration, and deployment efforts independently, collaborating with DFT teams, EDA vendors
• Drive new ATPG methodology, new tool evaluation, design DoEs, both within Qualcomm and partnering with EDA vendors.
• Develop optimized recipes for improving test quality, reducing test cost, DFT cycle time, pattern simulation runtimes.

Qualifications/Experience

• BE/B.Tech, ME/MTech/MS in Electrical/Electronics/Computer science Engineering
• 4-6 years demonstrated experience in VLSI EDA/CAD methodology development in areas of DFT, Scan/ATPG

Skills Required

• Strong knowledge of DFT domain specifically on Scan, ATPG and ATPG pattern simulations
• Strong development skills in TCL, Python
• Good understanding of SOC DFT Flow, ATE Flow and practices.
• Familiarity with standard software development process, systems including Configuration Management, QA, Release and Support
• Ability to plan and execute formal projects, deliverables.
• Ability to work with multiple WW teams in a fast paced and dynamic environment.
• Must be a team player, ability to multi-task, with attention to details.

Keywords:

DFT, ATPG, Scan, VLSI Test, Tessent, TetraMAX, TestMAX, MBIST, SMS

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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