General Summary:
· Experience in Power Analysis and optimization for complex data path oriented Multi-million gate designs. Working Knowledge on Primetime PTPX, RTL Power Pro and Power-Artist tools.
· Good working knowledge in multi-power domain structural power checks using CLP.
· Experience in generating SAIF files and working with Implementation teams for dynamic power optimizations
· Experience in identifying power optimization opportunities and articulate it with designers
· Good knowledge in generating and analyzing leakage at every implementation/Netlist stages
· Good team player. Need to interact with the stakeholders proactively
· Ability to debug and solve issues independently
Minimum Qualifications
· Bachelor's degree in Engineering, Electornics or related field.
· 3-5 years Hardware Engineering experience or related work experience
Minimum Qualifications:
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