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We are now looking for a DFT Verification Engineer. Design-for-Test (DFT) Engineering at NVIDIA works on groundbreaking innovations every day involving crafting creative solutions for DFT architecture, implementation, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We use the best industry tools and go beyond with internal methodologies to address some of NVIDIA's unique challenges. We are looking for you to implement the best verification methodologies for DFT IP at unit and system levels. You will bring in expertise in SystemVerilog, UVM, FPGA and Emulation application in DFT domain.
What you'll be doing
As a member of our team, You will build "state of the art" verification test benches and methodologies to verify DFT features in complex IP's/Sub-systems/SOC's.
Develop and own verification environment using UVM or equivalent.
Your responsibility will include to build reusable bus functional models, monitors, checkers and scoreboards.
Own functional coverage driven verification closure and own design verification sign-offs at multiple levels.
Collaborate closely with multi-functional teams like chip architecture, ASIC design, functional verification, and post silicon teams.
Will be part of innovation to strive to improve the quality of DFT methods
What we need to see
BSEE with 3+ or MSEE with 2+ years of experience in DFT verification or related domains.
Expertise in System Verilog and verification methodologies like UVM/VMM.
Expertise in prototyping, verification and debug tools (Emulation, FPGA, VCS, Debussy, Formality, PrimeTime etc).
Good exposure to ASIC design methodologies: RTL design, clocking, timing and low-power architectures.
Strong programming/scripting skills in C++, Perl, Python or Tcl
Excellent written and oral communication skills
Excitement to work on rare challenges
Strong analytical and problem solving skills
Ways to stand out from the crowd
Strong experience or interest in both DFT and RTL Verification domains
Knowledge in Formal verification methodologies and tools for IP and SoC level verification
Hands-on experience in post silicon debug on ATE and/or system labs.