ASIC Design Verification Engineer - ( SystemVerilog, UVM test bench, C/C++ , Perl/Python scripting, (VCS, DVE, Verdi), TCL/Shell scripting) | 5+ years

Join our dynamic front-end design team at Cisco Silicon One, where innovation meets

innovative technology! As part of the heart of silicon development at Cisco, you'll

engage in every facet of chip design, from architecture to validation, using the latest

silicon technologies to create groundbreaking devices.

Cisco Silicon One is the only unified silicon architecture that empowers customers to deploy top-tier silicon across diverse applications, from top-of-rack switches to expansive data centres. Be a part of shaping Cisco's progressive solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all aspects of our systems, using the latest technology.

We're seeking a dedicated ASIC engineer with a proven track record in high-performance products, ready to make a significant impact in the industry. Join us and push the boundaries of what's possible!

• Develop test plans, cover points, and qualification tests
• Perform end-to-end verification of design blocks and top-level
• Build and maintain block, cluster, and top-level DV environment infrastructure
• Construct testbenches components like scoreboard, agents, sequencers, and
• monitors
• Write tests, debug regressions, and drive to module verification closure
• Collaborate with designers and verification engineers for cross-block verification
• Upgrade configuration/reset sequences (APIs)
• Develop environment and tests for emulation
• Ensure complete verification coverage through code, functional coverage, and gate level simulations
• Support post-silicon bring-up and optimize integration and performance

• Bachelor’s Degree in EE, CE, or other related fields with 6+ years or Master’s Degree
• with 4+ years of ASIC design or verification experience
• Experience in developing verification environment for complex blocks from design specifications document
• Proficient in verifying complex blocks and/or clusters for ASIC using UVM/System Verilog.
• Scripting experience with Perl, Python, TCL, shell scripts.

• Experience in Data center/ Hyper scaler /AI Networking technologies
• Proven experience meeting and delivering project milestones and deadlines.
• Ability to communicate technical concepts to audiences spanning executives to junior
• engineers to customers.
• Demonstrated ability in troubleshooting and debugging.
• Experience with Emulation and Formal Verification tools is a plus.

#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.

We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do!

Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!