General Summary:
Skills & Experience
MTech/BTech in EE/CS with 12+ years of ASIC design experience.
Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA
Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5/6) is added advantage.
Understanding of protocols like AHB/AXI/ACE/CHI is desirable.
Experience with post-silicon bring-up and debug is a plus.
Able to work with teams across the globe and possess good communication skills.
Hands on experience in Multi Clock designs, Asynchronous interface is a must.
Hands on experience in Low power SoC design is required.
Responsibilities
Mirco architecture & RTL development and its validation for linting, clock-domain crossing and DFT rules.
Work with functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels.
Hands on experience in constraint development and timing closure.
UPF writing, power aware equivalence checks and low power checks.
Support performance debugs and address performance bottle necks.
Provide support to sub-system, SoC integration and chip level debug.
Minimum Qualifications:
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